Conclusion

    The project was accomplished ahead of schedule and all the tasks were fulfilled. The comparison between Project 27 (50% Hf) indicates that a higher oxide permittivity will show some of the positive effect on MOS capacitor, but negative side should not be ignored. Further research need to target on the fixed oxide charge density and try to decrease it.

    Apart from the general calculation, a MatLab program was written to calculate the electrical properties of the high-k gate stacks, The output result is shown below:

    The program needs to input the Capacitance, Voltage and Resistance data for calculation. Therefore, it can be used to calculate other gate materials with input data. If you are interested in the source code, please contact us.

Question 9. Compare the Results with Project 27 (50% Hf)

    Finally the results were compared with Project 27 (50% Hf). All the results between two groups are summarized below:

	Project 26 (70% Hf)	Project 27 (50% Hf)
Type of Substrate	P-type	P-type
Oxide Relative Permittivity	10.64	8.67
EOT (nm)	2.81	3.04
Doping Density (m-3)	4.244x1021	2.7x1021
Work Function Difference (eV)	0.065	0.08
Flatband Voltage (V)	0.932	0.53
Midgap Voltage (V)	1.367	1.21
Oxide Charge Density (cm-3)
Flatband Condition	-6.660x1016	-3.23x1016
Mdigap Condition	-7.841x1016	-6.4x1016

    It can be noticed that a higher percentage of Hf will lead to a higher oxide relative permittivity. It could be explained by the fact that the relative permittivity of Hf is higher than SiO2. Also, the equivalent oxide thickness will be decreased. Nevertheless the EOT is still too large for commercial purpose (which should be less than 2 nm). Higher percentage of Hf will also lead to a higher doping density, which will then increase the cost of manufacture.

    Another thing should be considered is that the fixed oxide charge density almost doubled in flatband condition. According to our supervisor, the charge density should be controlled less than 1x10¹⁰ in order to get a better quality of CMOS. Thus further research should be carried out to decrease the amount of fixed oxide charge density.

Question 10. Write program for plotting the ideal high-frequency capacitance voltage plot.

    As mentioned above, there is a small number of negative charges in oxide, which need extra voltage to neutralize to reach the same capacitance according to the equation:

    According to the previous task, the differences between ideal value and real value can be calculated in flat-band and mid-gap conditions.

    As shown above, the two voltage difference are almost same. In fact, there do exist a constant voltage difference between ideal and real values at same capacitance.

Question 7. Calculate the mid-gap voltage

When gate voltage of this p-type gate is continuously increased to be positive(decreased to be negative for n type), majority carriers (holes in this case) are forced away from the surface of the semiconductor and form a depletion region, which is called depletion or mid-gap. 

Similarly to the flat-band c=voltage, the mid-gap voltage can be calculated indirectly by matching the capacitance at that moment with the datum given in 'HFCV_70%Hf.txt'. The total capacitance will be the oxide capacitance in series with the depletion capacitance.

    (1)

(2)

Therefore,

 (3)

To improve the accuracy, the slop k at the matched point can be calculated, and the mid-gap voltage will be:

  (4)

Finally, the value of flat-band voltage is found to be 1.366 V.

Question 6. Calculate the flat-band voltage

When gate voltage of this p-type gate is increased (decreased for n type), the accumulation capacitor is decreased which will in turn reduce the measured capacitance. When the gate voltage is zero for ideal case, the condition is thus called flat-band. However, in real cases, because of the exist of oxide charges, the gate voltage will be a complex function of oxide charges instead of zero.

Fortunately, the flat-band voltage can be calculated indirectly by matching the capacitance at that moment with the datum given in 'HFCV_70%Hf.txt'. The total capacitance will be the oxide capacitance in series with the Debye capacitance.

    (1)

        (2)

    (3)

According to the calculation, the result of C_FB is equal to 345.27pF. 

However, it is obviously inaccurate to just find the nearest capacitance point in datum and use its voltage as the flat-band voltage. To improve the accuracy, the slop k at the matched point can be calculated, and the flat-band voltage will be:

  (4)

Finally, the value of flat-band voltage is found to be 0.932 V.

Question 5. Calculate the Work Function Difference Assuming a Gold (Au) Gate.

    The following figure shows the energy-band diagram of three separated components form the MOS capacitor.[1]

    For the case of using a gold (Au) gate, ΦM is the work function of metal and ΦS is the work    function of semiconductor. Thus, ΦMS is the work function difference between the gate and semiconductor. 

         (1)

    where 

 (2)

    Xs is the Electron Affinity of the Si, the value of which is 4.14 eV.

    Eg is the Bandgap energy, the value of which is 1.12 eV.

    Φfp is the Fermi potential for p-type silicon.

    According to the formula:

(3)

    Thus,

   (4)

    Therefore

  (5)

Reference:

[1]	N. Arora, MOSFET Modeling For VLSI Simulation, Singapore: World Scientific Printers, 2007.

Question 8. Finding the Oxide Charge Density at the Flatband Condition and at the Midgap Condition

    Recall from the former discussion that the flatband voltage could be calculated by the following equation:

                                  (1)   

    Where 

      (2)

    Therefore, replacing equation 2 to equation 1, Q can be found to be:

  (3)

    i.e.

 (4)

    In mid gap condition, the ideal case for the mid gap voltage should be:

   (5)

    By replacing all the figures, the result for mid gap voltage is 0.454 V. Then the total charge can be calculated by:

(6)

    Thus, the charge density is

  (7)

Question 3. Find the equivalent oxide thickness (EOT)

    The equivalent oxide thickness (EOT) is defined as the thickness of SiO2 layer required to achieve the same capacitance density as high-k material. Therefore, using the formula:

 (1)

    Thus, the equivalent oxide thickness is found to be 2.81 nm.

Question 4. Determine the Doping Density of the Silicon Substrate

    Again, looking at the C-V plot for the MOS capacitor, the minimum capacitance, C_min is given as the series contribution of oxide and depletion capacitor, as

   (1)

    Also 

                  (2)

    C_dep can be expressed as follows:

   (3)

    Where

    (4)

    Replacing all the variables in Equation (1) to (4), the doping density of the silicon substrate is found to be:

   (5)

    Clearly, it cannot be solved by ordinary method, thus the MATLAB is used to solve the equation.The result is shown:

 (7)

    The detailed discussion will be given in the final report.

Question 2. Determine the oxide relative permittivity

    The oxide relative permittivity could be found by calculating the capacitance of the oxide. For a p‑type MOS capacitor, the oxide capacitance is measured in the strong accumulation region. At that region, the capacitance could be represented by equation:

                                 (1)

    For the reason that in the accumulation region the capacitance for C_acc is pretty large, which can be ignored, Thus, the capacitance measured in the accumulation region could be represented as:

                                              (2)

    Where:

                                                        (3)

                                                     

                 

    C_max equals to 2.919 nF, as indicated in the C-V plot and A_c is the area of the MOS capacitors with the diameter of 0.55 mm. The value of C_ox is 0.0123 Fm^-2.

    For the reason that high-k material will form two different layers of oxide, which are HfSiO and SiO2. The cross-sectional photo for the MOS capacitor is also shown in below:

Taken from [1]

    (The picture is only used to indicate the structure of the MOS capacitor, in other words, the figures for the thickness of the oxide should be ignored.)

    Thus the capacitance for oxide should be:

   (4)

    And by using formulas:

                                               (5)

    The equation (4) can be simplified to:

    (6)

    Replacing all the figures the results for the oxide relative permittivity is: 10.643.

Reference:

[1]  M, Wang et.al. (2004) "Electrical Performance Improvement in SiO/HfSiO High-k Gate Stack for

Advanced Low Power Device Application " 2004 IEEE International Conference on Integrated Circuit Design and Technology.

Question 1. Determine the Type of Substrate

    The type of substrate can be determined by the C-V plot for the gate MOSFET. The given data (in HFCV_70%Hf.txt) are imported into the MatLab 2013a and the C-V characters is shown below:

Figure 1 C-V plot for the gate stacks

    The figure indicates the relationship between high-frequency capacitance and voltage. The maximum capacitance occurs at gate voltage (V_g) at -1 V. The capacitance is 2.919 nF. The minimum capacitance occurs at gate voltage (V_g) at 2 V, the minimum capacitance is 53.4 pF. It can also be noticed that the capacitance of the gate decreases with the increasing gate voltage.

    From the plot it can be noticed that the accumulation region appears with a negative gate voltage applied to the gate stack, while the depletion region appears with a positive gate voltage. Thus the substance should be p-type.

Background of High-k Material

    Owing to the rapid development of technology, the transistor density continues with Moore's law, which means the transistor is scaling aggressively. 

    In order to have a higher gate capacitance, which will lead to a higher drive current and better performance, the thickness of the oxide layer is decreased. Today, the thickness of SiO₂ layer is reduced to 1.2nm,  the size of 4~5 atoms, which is hundredths of 30 years ago [1]. 

    However, it still cannot meet the human's demand of smaller devices. As the thickness of the gate oxide below 2 nm, leakage currents due to tunneling increase drastically, which will lead to much higher power consumption and reduce device reliability [2]. Also the effect of Boron penetration should not be ignored. Boron penetration is the penetration of the gate oxide by boron of heavily doped p-type substrate, which will impact the gate oxide reliability and device lifetime [3].

    An alternate way of increasing gate capacitance is replacing the silicon dioxide gate with a material which has a higher dielectric constant (a.k.a high-k material), as indicated in the formula below:

    (1)

    With the use of high-k material, a higher capacitance with the same oxide thickness will be produced, but causing a much smaller leakage current.

Reference:
[1] D. Misra, H. Iwai and H. Wong, “High-k Gate Dielectrics,” The Electrochemical Society Interface, pp. 30-34, 2006. 
[2] H. R. Huff and D. C. Gilmer, High dielectric constant materials, Berlin: Springer-Verlag, 2005.
[3] B.Kim, et al. "Impact of boron penetration on gate oxide reliability and device lifetime in p+-poly PMOSFETs," 1997.

Introduction of MOS Capacitor

    There are three regions of MOS capacitor: accumulation, depletion, and inversion. Besides, there are two special critical points between these three conditions: flat-band and threshold as shown in the Figure 1. 

    The Figure below shows the ideal C-V curve of a n-type substrate. The red line indicates the capacitance of MOS capacitor operating in high frequency condition (normally 1 MHz), while the blue line indicates the capacitance operation in low frequency condition (normally 1 Hz). 

    The curve of p-type is the same as n-type, but the sign of the applied gate voltage is inverted.

Figure 1 C-V curve of n-type MOS capacitor [1] 

Reference:

[1] “MOS capacitor | MOS capacitance C V curve,” Electrical Engineering, [Online]. Available: http://www.electrical4u.com/mos-capacitor-mos-capacitance-c-v-curve/. [Accessed 6 February 2014].

The General Information about the Blog

    This blog is used for Y2 Mini-Project 26, EEE department, University of Liverpool.

    The title of the project is Modelling Electrical Properties of the Thin High-k Gate Stacks (HfSiO, 70%Hf). 

    The research group consists of three students, which are, Kaibin Ji, Fan Hu and Yizhou Jiang.  Dr. Ivona Mitrovic is the supervisor of the project. This project will last for about 6 weeks, including a final report and a bench inspiration for assessment.

    The main object of the project is to find out the electrical properties of the thin high-k gate stacks (HfSiO 70% Hf), a new material may replace SiO2 in the future for gate stack of MOSFET. There are 10 tasks need to be completed in the future, the results will be posted in this blog later.

    If you have any questions or suggestions for the blog, please feel free to contact us.