Background of High-k Material

    Owing to the rapid development of technology, the transistor density continues with Moore's law, which means the transistor is scaling aggressively. 

    In order to have a higher gate capacitance, which will lead to a higher drive current and better performance, the thickness of the oxide layer is decreased. Today, the thickness of SiO₂ layer is reduced to 1.2nm,  the size of 4~5 atoms, which is hundredths of 30 years ago [1]. 

    However, it still cannot meet the human's demand of smaller devices. As the thickness of the gate oxide below 2 nm, leakage currents due to tunneling increase drastically, which will lead to much higher power consumption and reduce device reliability [2]. Also the effect of Boron penetration should not be ignored. Boron penetration is the penetration of the gate oxide by boron of heavily doped p-type substrate, which will impact the gate oxide reliability and device lifetime [3].

    An alternate way of increasing gate capacitance is replacing the silicon dioxide gate with a material which has a higher dielectric constant (a.k.a high-k material), as indicated in the formula below:

    (1)

    With the use of high-k material, a higher capacitance with the same oxide thickness will be produced, but causing a much smaller leakage current.

Reference:
[1] D. Misra, H. Iwai and H. Wong, “High-k Gate Dielectrics,” The Electrochemical Society Interface, pp. 30-34, 2006. 
[2] H. R. Huff and D. C. Gilmer, High dielectric constant materials, Berlin: Springer-Verlag, 2005.
[3] B.Kim, et al. "Impact of boron penetration on gate oxide reliability and device lifetime in p+-poly PMOSFETs," 1997.

Introduction of MOS Capacitor

    There are three regions of MOS capacitor: accumulation, depletion, and inversion. Besides, there are two special critical points between these three conditions: flat-band and threshold as shown in the Figure 1. 

    The Figure below shows the ideal C-V curve of a n-type substrate. The red line indicates the capacitance of MOS capacitor operating in high frequency condition (normally 1 MHz), while the blue line indicates the capacitance operation in low frequency condition (normally 1 Hz). 

    The curve of p-type is the same as n-type, but the sign of the applied gate voltage is inverted.

Figure 1 C-V curve of n-type MOS capacitor [1] 

Reference:

[1] “MOS capacitor | MOS capacitance C V curve,” Electrical Engineering, [Online]. Available: http://www.electrical4u.com/mos-capacitor-mos-capacitance-c-v-curve/. [Accessed 6 February 2014].

The General Information about the Blog

    This blog is used for Y2 Mini-Project 26, EEE department, University of Liverpool.

    The title of the project is Modelling Electrical Properties of the Thin High-k Gate Stacks (HfSiO, 70%Hf). 

    The research group consists of three students, which are, Kaibin Ji, Fan Hu and Yizhou Jiang.  Dr. Ivona Mitrovic is the supervisor of the project. This project will last for about 6 weeks, including a final report and a bench inspiration for assessment.

    The main object of the project is to find out the electrical properties of the thin high-k gate stacks (HfSiO 70% Hf), a new material may replace SiO2 in the future for gate stack of MOSFET. There are 10 tasks need to be completed in the future, the results will be posted in this blog later.

    If you have any questions or suggestions for the blog, please feel free to contact us.